1. Field of the Invention
The invention relates to an arrangement for addressing a MOS store consisting of MOS transistor storage cells, with the aid of address signals, wherein the address signals are amplified, inverted and intermediately stored, and the negated and non-negated address signals are fed to a decoder circuit which is connected to drive lines to the storage cells and which selects a drive line in dependence upon the applied address signals.
2. Description of the Prior Art
Arrangements for the addressing of MOS transistor storage cells are known. Usually the MOS transistor storage cells are combined to form a matrix and each storage cell is operated by a word line and a bit line. If, for example, a storage cell or a series of storage cells is to be selected, it is necessary to select a word and a bit line. This is carried out with the aid of address signals which are fed to an addressing arrangement. An addressing arrangement of this kind contains address buffer circuits which amplify, invert and intermediately store the incoming address signals. The address buffer circuits are then connected to the actual decoder circuit. In dependence upon the prevailing address signal combination, the decoder circuit selects one of the drive lines, thus bit or word lines, leading to the storage cells.
If, for example, a store consisting of storage cells is supplied with n address signals, 2.sup.n drive lines can be selected. The n address signals are presented to n address buffer circuits in which the n address signals are negated and intermediately stored. Each address buffer circuit possesses two outputs, one for the negated address signal and one for the non-negated address signal, so that the total number of buffer outputs is 2n. The 2n buffer outputs are connected to the decoder circuit. Here the decoder circuit consists of decoder sub-circuits, each of which is connected to a drive line. The decoder sub-circuits are each constructed from parallel-connected MOS transistors, the so-called decoder transistors, each decoder transistor of a decoder sub-circuit being supplied with the address signal in negated or non-negated form. The function of such decoder sub-circuits is known and therefore does not require to be explained. In decoder sub-circuits constructed in this way, n decoder transistors are required as every decoder sub-circuit is fed with n address signals in negated or non-negated form. The total number of decoder transistors finally amounts to n decoder transistors per decoder sub-circuit times 2.sup.n decoder sub-circuits. Thus each of the 2n buffer outputs is connected to 2.sup.n /2 decoder transistors.
Thus if 6 address signals are employed and thus 64 drive lines are provided, 6 .times. 2.sup.6 decoder transistors are required in the decoder circuit. The loading of every buffer output then amounts to 32 decoder transistors. Each increase in the storage capacity results in an increase in drive lines, address signals and decoder transistors. This produces an increase in the capacitive loading of the buffer outputs, but a reduction in the switching speed. In highly integrated storage modules having a high storage density in the cell field, the reduction in the switching speed occurs in that the space available for the decoder transistors in the decoder circuit is limited. Therefore it is only possible to use small decoder transistors with a correspondingly low output current.